Verification Engineer (Sub-system level + high Speed protocol)
Location | Bengaluru |
Experience | 8+ years |
Noticeperiod | 0-15 days |
Job Description:
- Develop and execute verification plans for sub-system level designs.
- Design and implement test benches using System Verilog and Universal Verification Methodology (UVM).
- Develop test cases to verify functionality, performance, and compliance with high-speed protocols.
- Conduct functional verification, including simulation, debugging, and coverage analysis.
- Collaborate with design teams to identify and resolve design issues.
- Perform gate-level simulations and analyze timing and power characteristics.
- Participate in design reviews and provide feedback on verification aspects.
- Contribute to the improvement of verification methodologies and best practice